In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, a semiconductor device to be tested is placed on a test head and is provided with test signals (test patterns) produced by a pattern generator in the semiconductor test system at its appropriate test pins at predetermined test timings. The semiconductor device under test produces output signals in response to the test signals which are received by the semiconductor test system. The output signals are strobed (sampled) by strobe signals at predetermined timings and are compared with expected output data to determine whether the semiconductor device functions correctly or not.
An example of the structure and operation of the semiconductor test system will be briefly explained with reference to FIG. 1. In the example of FIG. 1, a test processor 11 is a dedicated processor provided within the semiconductor test system for controlling the operation of the test system through a tester bus. Based on pattern data from the test processor 11, a pattern generator 12 provides timing data and waveform data to a timing generator 13 and a wave formatter 14, respectively. A test pattern is produced by the wave formatter 14 with use of the waveform data from the pattern generator 12 and the timing data from the timing generator 13, and the test pattern is supplied to a device under test (DUT) 19 through a pin electronics 20 and a test fixture 22.
An output signal of the DUT 19 is converted to a logic signal by an analog comparator 16 with reference to a predetermined threshold voltage levels. The logic signal is compared with expected value data from the pattern generator 12 by a logic (pattern) comparator 17. The result of the logic comparison is stored in a failure memory 18 to be used later in a failure analysis stage.
A pair of driver 15 and analog comparator 16 is configured in a manner shown in the pin electronics 20 for each test pin (tester channel) and is switched by switches (not shown) depending on whether the corresponding device pin is input or output. A large scale semiconductor test system has a large number of test pins, such as more than 256 test pins. Thus, in an actual test system, the pin electronics 20 includes a large number of such driver and comparator pairs as well as switches. The test fixture 22 is a mechanical block containing a large number of connectors such as pogo-pins, cables, and a board to interface between the pin electronics 20 and the DUT 19.
There is a type of semiconductor device which has two output terminals for producing differential output signals such as an ECL (Emitter Coupled Logic) device and an LVDS (Low Voltage Differential Signaling) device. Because the operation speed is very high, such as 3 GHz (gigahertz) or higher, these devices play an important role in an image processing, a video device, 3D graphic technology where large volume of data has to be transferred. Other example having a differential output is a serial communication device such as a serializer and a deserializer. A signal level (voltage swing) of these differential devices is small, thereby being susceptible to noise such as common mode voltage fluctuations. The present invention is directed to a comparator circuit for use in a semiconductor test system for testing differential output signals (balanced transmission signals) of such high speed differential devices.
In testing differential output signals of DUT, it is tested whether each of the output signals is proper or not as well as whether the differential output signals as a whole are proper or not. FIG. 2A shows an example of circuit configuration of a comparator circuit 36 in the conventional technology for one test channel of a semiconductor test system. The comparator circuit 36 compares differential output signals, i.e., balanced transmission signals from a DUT 19 by comparators 41 and 42 separately provided from one another, upon receiving the differential output signals 31 and 32, respectively from the DUT 19.
In this circuit configuration, the low/high evaluation of the DUT differential output signals is made through comparison with predetermined reference voltages V1 and V2 given to the corresponding comparators 41 and 42. The reference voltages V1 and V2 are variable voltages for defining threshold voltages of the comparators. Strobe signals are provided to the comparators to define the comparison timings by the comparators 41 and 42.
FIG. 2B shows an example of waveforms in the differential output signals 31 and 32. This example is introduced here for explaining the problem involved in the comparator circuit 36. When a common mode peak is generated by the effect such as noise or other causes, a peak will be detected as an abnormal signal at the output of one of the comparators when the peak exceeds the threshold voltage.
When this kind of DUT output waveform is generated, DUT is judged as defective in the single output test wherein only one of the output signals is evaluated. However, under the differential output situation, such a common mode noise is sometimes considered non-defective in a practical use. Thus, it is necessary to test the differential output signals with a more precise and detailed manner. However, in the conventional test method, the differential output test is difficult to perform, and DUTs are frequently determined as defective even though the DUTs should be acceptable.
To more completely test the differential output devices, a differential IC chip has been proposed in which one testing channel is comprised of a differential driver and a differential comparator (2001 ITC International Test Conference, pp 1128-1133). FIG. 3A shows a block diagram of such a differential comparator incorporated in the differential IC chip. The differential comparator consists of two single-ended comparators 45 and 46, one differential comparator 48, and a selector block 49. Control signals (Psel Nsel, Dsel) are used for selecting the desired comparator results.
ACHI and BCLO are the comparison results sent to the logic comparator in the test semiconductor system. ACHI output is used for checking the DUT output signal is “High” state, and BCLO is used for checking the DUT output signal is “Low” state. The single ended comparators 45 and 46 are used for positive and negative DUT output signals, respectively. The differential comparator 48 is used to compare the differential swing of the DUT outputs.
The differential IC chip of FIG. 3A will be effective when it is incorporated in the pin electronics of the semiconductor test system at an early stage of production of the test system. However, it is expensive to produce such custom IC chips through a semiconductor production process and requires a long turn around time before actual IC chips are produced. Further, there arise a case where a user wants to test a differential device by a test system existing in his laboratory where the test system is not provided with differential comparators. For replacing the overall pin electronics with a pin electronics block configured by the differential IC chips noted above, a large scale change is involved, which requires a user to pay a large amount of money. Moreover, the replacement of the overall pin electronics has to change the performance of the existing test system which requires a complete change in the test program and may produce test results inconsistent to the previous test results.
FIG. 3B shows an example of waveforms of differential output signals for explaining a further disadvantage of the differential IC chip of FIG. 3A. In this example, the common mode voltage of the differential output signals DUT-P and DUT-N changes at a time t from Vc1 to Vc2. Such a short term common voltage changes cannot be effectively detected by the comparator circuit of FIG. 3A. This is because the comparator 48 is configured by a preamplifier which is a DC differential amplifier. Since a differential amplifier detects the voltage difference between the two inputs, such a voltage shift in the common mode voltage from Vc1 to Vc2 cannot be detected because the voltage difference between the two signals is unchanged.
As has been described above, the differential comparators in the conventional technology are not suitable for accurately testing differential output signals of high speed and small voltage swing. The differential IC chip recently proposed as shown in FIG. 3A requires to produce a customer IC which is expensive and takes too long a time from a design stage to an actual production. It is also difficult to replace the circuit components in the existing test systems used by customers with new differential IC chips. Therefore, there is a need in the industry for new differential comparator with high speed performance, low cost and easy installation in the existing test system.